Radio frequency integrated circuit (rfic) charged-device model (cdm) protection

ABSTRACT

An apparatus is described. The apparatus includes an input device. The apparatus also includes a positive supply voltage pad. The apparatus further includes an input signal pad. The apparatus also includes a ground pad. The apparatus further includes charged-device model protection circuitry that protects the input device from electrostatic discharge. The charged-device model protection circuitry includes at least one of de-Q circuitry and a cascode device.

RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No.13/841,239 filed on Mar. 15, 2013, which is hereby incorporated byreference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to wireless devices forcommunication systems. More specifically, the present disclosure relatesto systems and methods for radio frequency integrated circuit (RFIC)charged-device model (CDM) protection.

BACKGROUND

Electronic devices (cellular telephones, wireless modems, computers,digital music players, Global Positioning System units, Personal DigitalAssistants, gaming devices, etc.) have become a part of everyday life.Small computing devices are now placed in everything from automobiles tohousing locks. The complexity of electronic devices has increaseddramatically in the last few years. For example, many electronic deviceshave one or more processors that help control the device, as well as anumber of digital circuits to support the processor and other parts ofthe device.

Amplifiers are commonly used in various electronics devices to providesignal amplification. Different types of amplifiers are available fordifferent uses. For example, a wireless communication device such as acellular phone may include a transmitter and a receiver forbi-directional communication. The receiver may utilize a low noiseamplifier (LNA), the transmitter may utilize a power amplifier (PA) andthe receiver and transmitter may both utilize variable gain amplifiers(VGAs).

Amplifiers may be fabricated with various integrated circuit (IC)processes. Sub-micron complementary metal oxide semiconductor (CMOS)fabrication processes are commonly used for radio frequency (RF)circuits in wireless devices and other electronic devices in order toreduce cost and improve integration. However, transistors fabricatedwith sub-micron CMOS processes typically have small physical dimensionsand are more susceptible to stress and possibly failure due toelectrostatic discharge (ESD). ESD is a sudden large and momentaryelectrical charge that may come from static electricity and/or othersources. It is desirable to effectively combat ESD while minimallyaffecting performance.

SUMMARY

An apparatus is described. The apparatus includes an input device, apositive supply voltage pad, an input signal pad, a ground pad andcharged-device model protection circuitry. The charged-device modelprotection circuitry protects the input device from electrostaticdischarge. The charged-device model protection circuitry includes atleast one of de-Q circuitry and a cascode device. The cascode device istriggered on by a trigger voltage.

The charged-device model protection circuitry may include de-Qcircuitry. The de-Q circuitry may include a resistor and a diode inseries. The input device may include an n-channel transistor. Theresistor may be coupled to a source of the re-channel transistor. Acathode of the diode may be coupled to a gate of the n-channeltransistor.

The de-Q circuitry may limit current through a parasitic path of there-channel transistor, reducing voltage buildup between the gate of then-channel transistor and the source of the n-channel transistor. Thede-Q circuitry may direct electrostatic discharge through a +ve diodecoupled between the ground pad and the input signal pad. The de-Qcircuitry may keep a voltage from the gate of the n-channel transistorto the source of the n-channel transistor less than a voltage differencebetween the input signal pad and a local ground node on the apparatus.

The charged-device model protection circuitry comprises a cascodedevice. The cascode device may turn on the input device during −veelectrostatic discharge. The cascode may include a first n-channeltransistor. A gate of the first n-channel transistor may be coupled toan RC clamp trigger voltage. A source of the first n-channel transistormay be coupled to a drain of the input device. Turning on the inputdevice may increase a source potential of the input device, protectingthe gate-to-source of the input device.

A method for electrostatic discharge protection is also described. A +vevoltage pulse is detected at a ground pad. Current is conducted througha +ve diode coupled between the ground pad and an input signal pad. Avoltage drop is generated across a degeneration inductor coupled betweenan input device and the ground pad. Current passing from a source of theinput device to a gate of the input device is limited using de-Qcircuitry. A voltage from the gate of the input device to the source ofthe input device is maintained that is below a failure point for theinput device.

A method for electrostatic discharge protection is described. A −vevoltage pulse is detected at an input signal pad. Current is conductedthrough a −ve diode coupled between the input signal pad and a localsupply node. The −ve current is steered to a ground pad via an RC clamp.A cascode device is turned on using an RC clamp trigger voltage from theRC clamp. An input device is turned on using the cascode device. Avoltage from a gate of the input device to a source of the input devicethat is below a failure point for the input device is maintained.

An apparatus for electrostatic discharge protection is also described.The apparatus includes means for detecting a +ve voltage pulse at aground pad. The apparatus also includes means for conducting currentthrough a +ve diode coupled between the ground pad and an input signalpad. The apparatus further includes means for generating a voltage dropacross a degeneration inductor coupled between an input device and theground pad. The apparatus also includes means for limiting currentpassing from a source of the input device to a gate of the input device.The apparatus further includes means for maintaining a voltage from thegate of the input device to the source of the input device that is belowa failure point for the input device.

An apparatus for electrostatic discharge protection is described. Theapparatus includes means for detecting a −e voltage pulse at an inputsignal pad. The apparatus also includes means for conducting currentthrough a −ve diode coupled between the input signal pad and a localsupply node. The apparatus further includes means for steering −vecurrent to a ground pad via an RC clamp. The apparatus also includesmeans for turning on a cascode device using an RC clamp trigger voltagefrom the RC clamp. The apparatus further includes means for turning onan input device using the cascode device. The apparatus also includesmeans for maintaining a voltage from a gate of the input device to asource of the input device that is below a failure point for the inputdevice.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a wireless device for use in the present systems andmethods;

FIG. 2 is a simplified circuit diagram of a radio frequency integratedcircuit (RFIC) receiver's low noise amplifier (LNA) that includes de-Qcircuitry;

FIG. 3 is a more detailed circuit diagram of a radio frequencyintegrated circuit (RFIC) receiver's low noise amplifier (LNA) thatincludes de-Q circuitry;

FIG. 4 is a graph illustrating +ve charged-device model (CDM) voltagesfor normal charged-device model (CDM) protection circuitry and forcharged-device model (CDM) protection circuitry that includes de-Qcircuitry, during a +ve charged-device model (CDM) test;

FIG. 5 is a flow diagram of a method for providing electrostaticdischarge (ESD) protection;

FIG. 6 is a circuit diagram of a radio frequency integrated circuit(RFIC) that includes a G1 cascode;

FIG. 7 is a more detailed circuit diagram of a radio frequencyintegrated circuit (RFIC) that includes a G1 cascode;

FIG. 8 is a graph illustrating -ye charged-device model (CDM) voltagesfor normal charged-device model (CDM) protection circuitry and forcharged-device model (CDM) protection circuitry that includes a G1cascode device;

FIG. 9 is a flow diagram of another method for providing electrostaticdischarge (ESD) protection;

FIG. 10 is a circuit diagram of a radio frequency integrated circuit(RFIC) that includes both de-Q circuitry and a G1 cascode device;

FIG. 11 is a more detailed circuit diagram of a radio frequencyintegrated circuit (RFIC) that includes a forward biased diode; and

FIG. 12 illustrates certain components that may be included within awireless device.

DETAILED DESCRIPTION

FIG. 1 shows a wireless device 102 for use in the present systems andmethods. The wireless device 102 may include a radio frequencyintegrated circuit (RFIC) 104 that includes advanced charged-devicemodel (CDM) protection circuitry 112. Advanced charged-device model(CDM) protection circuitry 112 may allow the radio frequency integratedcircuit (RFIC) 104 to pass charged-device model (CDM) testing withoutcompromising performance (e.g., by avoiding degrading input match, noisefigure (NF) or linearity).

A wireless device 102 may be a wireless communication device or a basestation. A wireless communication device may also be referred to as, andmay include some or all of the functionality of, a terminal, an accessterminal, a user equipment (UE), a subscriber unit, a station, etc. Awireless communication device may be a cellular phone, a personaldigital assistant (PDA), a wireless device, a wireless modem, a handhelddevice, a laptop computer, a PC card, compact flash, an external orinternal modem, a wireline phone, etc. A wireless communication devicemay be mobile or stationary. A wireless communication device maycommunicate with zero, one or multiple base stations on a downlinkand/or an uplink at any given moment. The downlink (or forward link)refers to the communication link from a base station to a wirelesscommunication device, and the uplink (or reverse link) refers to thecommunication link from a wireless communication device to a basestation. Uplink and downlink may refer to the communication link or tothe carriers used for the communication link.

A wireless communication device may operate in a wireless communicationsystem that includes other wireless devices 102, such as base stations.A base station is a station that communicates with one or more wirelesscommunication devices. A base station may also be referred to as, andmay include some or all of the functionality of, an access point, abroadcast transmitter, a Node B, an evolved Node B, etc. Each basestation provides communication coverage for a particular geographicarea. A base station may provide communication coverage for one or morewireless communication devices. The term “cell” can refer to a basestation and/or its coverage area, depending on the context in which theterm is used.

Communications in a wireless communication system (e.g., amultiple-access system) may be achieved through transmissions over awireless link. Such a communication link may be established via asingle-input and single-output (SISO) or a multiple-input andmultiple-output (MIMO) system. A multiple-input and multiple-output(MIMO) system includes transmitter(s) and receiver(s) equipped,respectively, with multiple transmit antennas (NT) and multiple receiveantennas (NR) for data transmission. SISO systems are particularinstances of a multiple-input and multiple-output (MIMO) system. Themultiple-input and multiple-output (MIMO) system can provide improvedperformance (e.g., higher throughput, greater capacity or improvedreliability) if the additional dimensionalities created by the multipletransmit and receive antennas are utilized.

The wireless communication system may utilize both single-input andmultiple-output (SIMO) and multiple-input and multiple-output (MIMO).The wireless communication system may be a multiple-access systemcapable of supporting communication with multiple wireless communicationdevices by sharing the available system resources (e.g., bandwidth andtransmit power). Examples of such multiple-access systems include codedivision multiple access (CDMA) systems, wideband code division multipleaccess (W-CDMA) systems, time division multiple access (TDMA) systems,frequency division multiple access (FDMA) systems, orthogonal frequencydivision multiple access (OFDMA) systems, single-carrier frequencydivision multiple access (SC-FDMA) systems, 3 ^(rd) GenerationPartnership Project (3GPP) Long Term Evolution (LTE) systems and spatialdivision multiple access (SDMA) systems.

The wireless device 102 may include a radio frequency integrated circuit(RFIC) 104. The radio frequency integrated circuit (RFIC) 104 mayinclude radio frequency (RF) components, such as an input device 128.One example of an input device 128 is an amplifier. An amplifier may bea low noise amplifier (LNA), a direct amplifier (DA) or a poweramplifier (PA). An input device 128 (such as a low noise amplifier(LNA)) may have internal matching. An amplifier on a radio frequencyintegrated circuit (RFIC) 104 may receive input signals from devicesthat are external to the radio frequency integrated circuit (RFIC) 104(such as a modem or an antenna on the wireless device 102). Thus, theinput device 128 may have inputs coupled to integrated circuit (IC)pins. In one configuration, the input device 128 may be coupled tomultiple IC pins (e.g., a positive supply voltage pad 106, an inputsignal pad 108 and a ground pad 110). These IC pins may be susceptibleto electrostatic discharge (ESD), which may damage the circuits (e.g.,the input device 128) coupled to the IC pins.

To avoid damage to the input device 128 by electrostatic discharge(ESD), the radio frequency integrated circuit (RFIC) 104 may includecharged-device model (CDM) protection circuitry 112. The charged-devicemodel (CDM) protection circuitry 112 may provide protection for +vecharged-device model (CDM) testing and −ve charged-device model (CDM)testing. The charged-device model (CDM) protection circuitry 112 mayinclude an RC clamp 120, a +ve diode 124 and a −ve diode 122. All diodesused herein may be gated diodes or shallow trench isolation (STI)diodes. The charged-device model (CDM) protection circuitry 112 may alsoinclude de-Q circuitry 114 and a G1 cascode device 126. The de-Qcircuitry 114 may be current limiting circuitry.

During the initial setup of charged-device model (CDM) testing, thedevice under test (DUT), which is the radio frequency integrated circuit(RFIC) 104 in this case, is placed on an insulated field plate, which ischarged to a certain voltage. Typically, this voltage is +500 volts (V)or −500 V, which ensures that the radio frequency integrated circuit(RFIC) 104 is robust against most of the electrostatic discharge (ESD)events generated during automated assembly. The ground plane of theradio frequency integrated circuit (RFIC) 104 also requires the sametest voltage as the field plate, and there is not a charge storedbetween the radio frequency integrated circuit (RFIC) 104 and the fieldplate. During the testing phase, one of the pins on the radio frequencyintegrated circuit (RFIC) 104 is shorted to ground. At that instance,the potential difference between the shorted pin and the ground planeequals the test voltage, which can damage the low power devices on theradio frequency integrated circuit (RFIC) 104. The inputs to a low noiseamplifier (LNA) are particularly vulnerable, as in the common sourceconfiguration, the transistor gate is coupled to the input pad while thesource is coupled to the ground pad. Hence, potential quickly developsacross the gate-oxide, which can damage the transistor. Thus, additionalelectrostatic discharge (ESD) circuitry may be required to prevent suchdamage and facilitate a low impedance path for the discharge current.

In +ve charged-device model (CDM) testing, the electrostatic discharge(ESD) current path is from the ground pad 110 to the input signal pad108. In −ve charged-device model (CDM) testing, the electrostaticdischarge (ESD) current path is from the input signal pad 108 to thenegatively charged ground pad 110. For typical radio frequencyintegrated circuit (RFIC) 104 chip sizes and charged-device model (CDM)testers, a peak discharge current of approximately 5 amperes (A) isexpected for the +/− 500 V test. A diode 122, 124 in the charged-devicemodel (CDM) protection circuitry 112 may clamp the voltage atapproximately 3 V for 5 A of peak charged-device model (CDM) testing.

In current understandings, the resistance in the electrostatic discharge(ESD) path is kept at below 0.5 ohms (i.e., a voltage drop of less than2.5 V for 5 A of current). Thus, the total voltage across the inputdevice 128 (e.g., from the gate to source of a transistor in the inputdevice 128) may be approximately 5.5 V (the breakdown of the inputdevice 128 is dependent on the technology used). By keeping theresistance in the +ve electrostatic discharge (ESD) path below 0.5 ohmsand sizing the +ve diode 124 appropriately, the +ve 500 V charged-devicemodel (CDM) test can easily be passed. Likewise, by keeping theresistance in the −ve electrostatic discharge (ESD) path below 0.5 ohmsand sizing both the RC clamp 120 and the −ve diode 122 appropriately,the −ve 500 V charged-device model (CDM) test can easily be passed.

To further improve the charged-device model (CDM) protection circuitry112 for +ve charged-device model (CDM) testing, the charged-device model(CDM) protection circuitry 112 may include de-Q circuitry 114. The de-Qcircuitry 114 may include a resistor 116 and a diode 118. The diode 118may be reverse biased during normal operation, with a negligible impacton the receiver performance. Due to the design of the charged-devicemodel (CDM) protection circuitry 112, resonance may occur between thegate-source capacitance of the input device 128 and the sourcedegeneration inductance during +ve charged-device model (CDM) testing,causing failures of the input device 128 at lower than expected +vecharged-device model (CDM) voltages (causing the radio frequencyintegrated circuit (RFIC) 104 to fail the +ve charged-device model (CDM)test). The de-Q circuitry 114 may prevent this resonance from occurring.The de-Q circuitry 114 is discussed in additional detail below inrelation to FIG. 2.

To further improve the charged-device model (CDM) protection circuitry112 for −ve charged-device model (CDM) testing, the charged-device model(CDM) protection circuitry 112 may also include a G1 cascode device 126.During a −ve charged-device model (CDM) test, larger voltages are builtup across the gate and source of the input device 128 than during a +vecharged-device model (CDM) test, since the charged-device model (CDM)discharge must flow through the −ve diode 122, the RC clamp 120 andparasitic inductances. This increased voltage may cause the input device128 to fail during a −ve charged-device model (CDM) test (thus causingthe radio frequency integrated circuit (RFIC) 104 to fail the −vecharged-device model (CDM) test). The G1 cascode device 126 may betriggered by an RC clamp trigger voltage from the RC clamp 120. When theG1 cascode device 126 is triggered, the G1 cascode device 126 willdirectly couple the drain of the input device 128 to the voltage Vdd,and hence put the input device 128 in saturation, thus providingadditional protection during the −ve charged-device model (CDM) test.The G1 cascode device 126 is discussed in additional detail below inrelation to FIG. 6.

FIG. 2 is a simplified circuit diagram of a radio frequency integratedcircuit (RFIC) 204 receiver's low noise amplifier (LNA) that includesde-Q circuitry 214. The radio frequency integrated circuit (RFIC) 204 ofFIG. 2 may be one configuration of the radio frequency integratedcircuit (RFIC) 104 of FIG. 1. The radio frequency integrated circuit(RFIC) 204 may be a receiver low noise amplifier (LNA). The radiofrequency integrated circuit (RFIC) 204 of FIG. 2 does not includemodels of parasitics that may occur in the radio frequency integratedcircuit (RFIC) 204. The radio frequency integrated circuit (RFIC) 204may include an amplifier 228 (i.e., an input device 128), a positivesupply voltage pad 206, an input signal pad 208, a ground pad 210, a +vediode 224, a −ve diode 222, an RC clamp 220, a load inductor 234 and adegeneration inductor 238. The amplifier 228 may include a firstn-channel transistor 230 and a second n-channel transistor 232. In someconfigurations, the second re-channel transistor 232 may be referred toas the main cascode device.

The drain of the second n-channel transistor 232 may be coupled to alocal supply node 236 via the load inductor 234. Between the loadinductor 234 and the drain of the second n-channel transistor 232 is theoutput 235 of the radio frequency integrated circuit (RFIC) 204, whichmay be provided to a downconverter. The local supply node 236 may becoupled to the positive supply voltage pad 206. The cathode of the −vediode 222 may be coupled to the local supply node 236. The anode of the−ve diode 222 may be coupled to the input signal pad 208. The ground pad210 may be coupled to a local ground node 240. The anode of the +vediode 224 may also be coupled to the local ground node 240. The cathodeof the +ve diode 224 may be coupled to the input signal pad 208. Theinput signal pad 208 may also be coupled to the gate of the firstn-channel transistor 230.

The drain of the first n-channel transistor 230 may be coupled to thesource of the second n-channel transistor 232. The gate of the secondn-channel transistor 232 may be coupled to DC bias circuitry (notshown). The source of the first n-channel transistor 230 may be coupledto the local ground node 240 via the degeneration inductor 238. The RCclamp 220 may be coupled between the local supply node 236 and the localground node 240. The body of the first n-channel transistor 230 may alsobe coupled to the anode of a parasitic diode PW 254. The cathode of theparasitic diode PW 254 may be coupled to the source of the firstn-channel transistor 230.

The de-Q circuitry 214 may include a resistor 216 and a diode 218 inseries. The diode 218 may be a gated diode or a shallow trench isolation(STI) diode. The diode 218 may be reverse biased during normaloperation, with a negligible impact on the receiver performance. Theresistor 216 may be coupled between the source of the first n-channeltransistor 230 and the anode of the diode 218. The cathode of the diode218 is coupled to the gate of the first n-channel transistor 230.Parasitics (such as parasitic capacitances, parasitic resistances andparasitic inductances) inherent in the radio frequency integratedcircuit (RFIC) 204 are illustrated in FIG. 3 and left out of FIG. 2 forsimplicity. The function of the de-Q circuitry 214 is discussed below inrelation to FIG. 3.

FIG. 3 is a more detailed circuit diagram of a radio frequencyintegrated circuit (RFIC) 304 receiver's low noise amplifier (LNA) thatincludes de-Q circuitry 314. Specifically, the radio frequencyintegrated circuit (RFIC) 304 of FIG. 3 includes parasitics that areinherent in an integrated circuit. The radio frequency integratedcircuit (RFIC) 304 may be a receiver low noise amplifier (LNA). Theradio frequency integrated circuit (RFIC) 304 may include an amplifier328 (i.e., an input device 128 as shown in FIG. 1), a positive supplyvoltage pad 306, an input signal pad 308, a ground pad 310, a +ve diode324, a −ve diode 322, an RC clamp 320, a load inductor 334 and adegeneration inductor 338. The amplifier 328 may include a firstre-channel transistor 330 and a second n-channel transistor 332. In someconfigurations, the second n-channel transistor 332 may be referred toas the main cascode device. The parasitics illustrated in FIG. 3 areonly models and do not represent actual components within the radiofrequency integrated circuit (RFIC) 304. The main charged-device model(CDM) current discharge path 348 for the +ve charged-device model (CDM)test voltage is illustrated from the ground pad 310 to the input signalpad 308.

The load inductor 334 may be coupled between the drain of the secondre-channel transistor 332 and a local supply node 336. Between the loadinductor 334 and the drain of the second n-channel transistor 332 is theoutput 335 of the radio frequency integrated circuit (RFIC) 304, whichmay be provided to a downconverter. The local supply node 336 may becoupled to the positive supply voltage pad 306 via a coupling wire thatincludes a parasitic resistance 344 a and a parasitic inductance 346 a.Because the die area occupied by the passive components in an integratedcircuit (e.g., the inductors) are typically much larger than that of theactive components (e.g., the transistors), the wires used to couplecomponents on the radio frequency integrated circuit (RFIC) 304 mayinclude significant parasitic resistance 344 and significant parasiticinductance 346 (depending on the length of coupling wires).

The cathode of the −ve diode 322 may be coupled to the local supply node336 via a coupling wire that includes a parasitic inductance 346 b and aparasitic resistance 344 b. The anode of the −ve diode 322 may becoupled to the input signal pad 308. The voltage at the input signal pad308 may be referred to as the voltage Vin. The input signal pad 308 mayalso be coupled to the cathode of the +ve diode 324. The anode of the+ve diode 324 may be coupled to a local ground node 340 via a couplingwire that includes a parasitic resistance 344 c and a parasiticinductance 346 c. The node at the anode of the +ve diode 324 may bereferred to as the diode ground node 347. The voltage at the localground node 340 may be referred to as Vgnd.

The ground pad 310 may be coupled to the local ground node 340 via acoupling wire that includes a parasitic resistance 344 d and a parasiticinductance 346 d. The degeneration inductor 338 may be coupled betweenthe local ground node 340 and the source of the first n-channeltransistor 330. The input signal pad 308 may also be coupled to the gateof the first n-channel transistor 330. The body of the first n-channeltransistor 330 may also be coupled to the anode of a parasitic diode PW354. The cathode of the parasitic diode PW 354 may be coupled to thesource of the first n-channel transistor 330. This diode 354 representsthe p-n junction formed between the p-type body and the n+ source. Thefirst n-channel transistor 330 may be placed in a deep n-well. In thisscenario, the body of the first n-channel transistor 330 may be coupledto the anode of a parasitic diode DNW 356. The cathode of the parasiticdiode DNW 356 may be coupled to the local supply node 336. Here, theparasitic diode DNW 356 represents the p-n junction diode formed betweenthe p-type body and the n-type nwell. The body of the first n-channeltransistor 330 may be coupled to the local ground node 340 via acoupling wire that includes a parasitic resistance 344 e and a parasiticinductance 346 e.

The anode of a parasitic diode psub 358 may be coupled to the diodeground node 347. The cathode of the parasitic diode psub 358 may becoupled to the cathode of the parasitic diode DNW 356. Here, theparasitic diode psub 358 represents the p-n junction diode formedbetween the p-type substrate and the deep nwell.

The drain of the first n-channel transistor 330 may be coupled to thesource of the second n-channel transistor 332. The source of the firstn-channel transistor 330 may be coupled to the degeneration inductor338. The RC clamp 320 may be coupled between the local supply node 336and the local ground node 340. A parasitic capacitance Cgs 342, whichrepresents the gate-source capacitance, may occur between the gate ofthe first n-channel transistor 330 and the source of the first n-channeltransistor 330. Without the de-Q circuitry 314, the degenerationinductor 338 and the parasitic capacitance Cgs 342 may resonate,generating a higher voltage across the parasitic capacitance Cgs 342than the potential building up between the voltage Vin at the inputsignal pad 308 and the voltage Vgnd at the local ground node 340,causing failures of the input device 128 at lower than expected +vecharged-device model (CDM) voltages.

The de-Q circuitry 314 may include a resistor 316 and a diode 318 inseries. The diode 318 may be reverse biased during normal operation,with a negligible impact on the receiver performance. The resistor 316may be coupled between the source of the first n-channel transistor 330and the anode of the diode 318. The cathode of the diode 318 may becoupled to the gate of the first n-channel transistor 330. The mainpurpose of the resistor 316 and the diode 318 is to reduce the resonancebetween the parasitic capacitance Cgs 342 and the degeneration inductor338 by rendering the source as a low impedance node. Typically, priorart teaches to limit resistance in the +ve charged-device model (CDM)path. This is done to limit the gate-to-source voltage of the inputdevice 128 (e.g., the first n-channel transistor 330). Thus, the priorart teaches away from adding a resistor 316 between the gate and sourceof the first n-channel transistor 330. Putting a diode alone between thesource and gate of the first n-channel transistor 330 will allowsignificant current to pass through, which necessitates a larger diodeto handle the current. Adding resistance limits the current, and thusenables the use of a very small diode 318, which has negligible impacton performance.

The gate to source of the first n-channel transistor 330 may be modeledas a capacitor 342 in series with the degeneration inductor 338. Duringan electrostatic discharge (ESD) event, the capacitor 342 in series withthe degeneration inductor 338 may resonate, building up a voltage Vgsfrom the gate-to-source of the first n-channel transistor 330 that ishigher than the voltage difference between Vin and the local ground node340 Vin−Vgnd. This higher voltage may cause the first n-channeltransistor 330 to fail.

The de-Q circuitry 314 limits current through the parasitic path (fromthe source of the first n-channel transistor 330 to the gate of thefirst n-channel transistor 330 via the parasitic capacitance Cgs 342),enabling the use of a smaller diode 318 to minimize the parasiticcapacitance Cgs 342. Because current cannot travel through the de-Qcircuitry 314, the de-Q circuitry 314 (including the resistor 316)reduces the voltage Vgs from the gate of the first n-channel transistor330 to the source of the first n-channel transistor 330 (and forces thecurrent to go through the actual electrostatic discharge (ESD)protection path (i.e., the +ve diode 324)), thereby keeping the voltageVgs below Vin−Vgnd. This is illustrated in FIG. 4. Keeping the voltageVgs below Vin−Vgnd avoids failures of the first n-channel transistor 330due to the +ve charged-device model (CDM) path.

FIG. 4 is a graph illustrating +ve charged-device model (CDM) voltagesfor normal charged-device model (CDM) protection circuitry and forcharged-device model (CDM) protection circuitry 112 that includes de-Qcircuitry 114, during a +ve charged-device model (CDM) test. In thenormal charged-device model (CDM) protection circuitry, during +vecharged-device model (CDM) testing, the voltage Vgs 450 a swings muchhigher than Vin−Vgnd 452 a, resulting in failure of the first re-channeltransistor 330. In the charged-device model (CDM) protection circuitry112 that includes de-Q circuitry 114, during charged-device model (CDM)testing, the voltage Vgs 450 b is always less than Vin−Vgnd 452 b (andthus less than the breakdown voltage), preventing failure of the firstn-channel transistor 330.

FIG. 5 is a flow diagram of a method 500 for providing electrostaticdischarge (ESD) protection. Specifically, the method 500 may provideelectrostatic discharge (ESD) protection for +ve charged-device model(CDM) testing. The method 500 may be performed by a radio frequencyintegrated circuit (RFIC) 104 that includes charged-device model (CDM)protection circuitry 112. The charged-device model (CDM) protectioncircuitry 112 may include de-Q circuitry 114. The de-Q circuitry 114 mayinclude a resistor 116 and a diode 118.

The radio frequency integrated circuit (RFIC) 104 may detect 502 a +vecharged-device model (CDM) voltage difference between the ground pad 110and the input pad 108. The radio frequency integrated circuit (RFIC) 104may conduct 504 current through a +ve diode 124 coupled between theground pad 110 and an input signal pad 108. The radio frequencyintegrated circuit (RFIC) 104 may generate 506 a voltage drop across adegeneration inductor 338 coupled between an input device 128 and theground pad 110. The potential difference between the ground pad 110 andthe input pad 108 may create resonance between the parasitic capacitanceCgs 342 and the degeneration inductor 338. The resonance may create alarge swing at the source node. The radio frequency integrated circuit(RFIC) 104 may limit reduce 508 the resonance by limiting currentpassing from the source of the input device 128 to the gate of the inputdevice 128 using the de-Q circuitry 114. The radio frequency integratedcircuit (RFIC) 104 may maintain 510 a voltage Vgs from the gate of theinput device 128 to the source of the input device 128 that is below thefailure point of the input device 128 (i.e., approximately 7 V).

FIG. 6 is a circuit diagram of a radio frequency integrated circuit(RFIC) 604 that includes a G1 cascode device 626. The radio frequencyintegrated circuit (RFIC) 604 of FIG. 6 may be one configuration of theradio frequency integrated circuit (RFIC) 104 of FIG. 1. The radiofrequency integrated circuit (RFIC) 604 may be a receiver low noiseamplifier (LNA). The radio frequency integrated circuit (RFIC) 604 ofFIG. 6 does not include models of parasitics that may occur in anintegrated circuit. The radio frequency integrated circuit (RFIC) 604may also include an amplifier 628 (i.e., an input device 128), apositive supply voltage pad 606, an input signal pad 608, a ground pad610, a +ve diode 624, a −ve diode 622, an RC clamp 620, a load inductor634 and a degeneration inductor 638. The amplifier 628 may include afirst n-channel transistor 630 and a second n-channel transistor 632.The second re-channel transistor 632 may be referred to as the maincascode device.

The drain of the second n-channel transistor 630 may be coupled to theload inductor 634. Between the load inductor 634 and the drain of thesecond n-channel transistor 632 is the output 635 of the radio frequencyintegrated circuit (RFIC) 604, which may be provided to a downconverter.The load inductor 634 may be coupled to a local supply node 636. Thepositive supply voltage pad 606 may also be coupled to the local supplynode 636. The cathode of the −ve diode 622 may further be coupled to thelocal supply node 636. The anode of the −ve diode 622 may be coupled tothe input signal pad 608. The input signal pad 608 may also be coupledto the cathode of the +ve diode 624. The anode of the +ve diode 624 maybe coupled to a local ground node 640. The ground pad 610 may also becoupled to the local ground node 640. The input signal pad 608 mayfurther be coupled to the gate of the first n-channel transistor 630.The degeneration inductor 638 may be coupled between the source of thefirst n-channel transistor 630 and the local ground node 640.

The drain of the first n-channel transistor 630 may be coupled to thesource of the second n-channel transistor 632. The gate of the secondn-channel transistor 632 may be coupled to a DC biasing voltage. The RCclamp 620 may be coupled between the local supply node 636 and the localground node 640.

The drain of the G1 cascode device 626 may be coupled to the localsupply node 636 (the G1 cascode device 626 may be an n-channeltransistor). The source of the G1 cascode device 626 may be coupled tothe source of the second n-channel transistor 632. The gate of the G1cascode device 626 may be coupled to an RC clamp trigger voltage 660provided by the RC clamp 620. The function of the G1 cascode device 626in the radio frequency integrated circuit (RFIC) 604 during a +vecharged-device model (CDM) test is discussed below in relation to FIG.7.

During −ve charged-device model (CDM) testing, the gate of the firstre-channel transistor 630 is at a higher potential than the drain andsource of the first re-channel transistor 630. The drain and source ofthe first n-channel transistor 630 eventually get charged through thelocal ground node 640 (with current coming through the RC clamp 620). Byadding the G1 cascode device 626, another discharge path is created,which goes through the main device (the first n-channel transistor 630)itself. As the G1 cascode device 626 pulls the drain of the firstn-channel transistor 630 up to the same potential as the local supplynode 636, the potential at the drain of the first re-channel transistor630 is only one diode drop (the −ve diode 622) away from the potentialof the gate of the first n-channel transistor 630. Thus, the firstn-channel transistor 630 gets forward biased, creating both anadditional path for charging the local ground node 640 and reducing thegate to drain voltage and gate to source voltage for the first n-channeltransistor 630, thus improving the charged-device model (CDM)performance. In other words, the G1 cascode device 626 may be anycircuit that can create low impedance between the local supply node 636and the local ground node 640 when the RC clamp trigger voltage 660 ishigh. Thus, although an n-channel transistor is shown as the G1 cascodedevice 626, other circuitry may also be used to implement the G1 cascodedevice 626.

FIG. 7 is a more detailed circuit diagram of a radio frequencyintegrated circuit (RFIC) 704 that includes a G1 cascode. Specifically,the radio frequency integrated circuit (RFIC) 704 of FIG. 7 includesparasitics that are inherent in an integrated circuit. The radiofrequency integrated circuit (RFIC) 704 may be a receiver low noiseamplifier (LNA). The radio frequency integrated circuit (RFIC) 704 mayinclude an amplifier 728 (i.e., an input device 128), a positive supplyvoltage pad 706, an input signal pad 708, a ground pad 710, a +ve diode724, a −ve diode 722, an RC clamp 720, a G1 cascode device 726, a loadinductor 734 and a degeneration inductor 738. The amplifier 728 mayinclude a first n-channel transistor 730 and a second re-channeltransistor 732. The second n-channel transistor 732 may be referred toas the main cascode device. The parasitics illustrated in FIG. 7 areonly models and do not represent actual components within the radiofrequency integrated circuit (RFIC) 704. The -ye charged-device model(CDM) path 762 is illustrated from the input signal pad 708 to theground pad 710.

The load inductor 734 may be coupled between the drain of the secondre-channel transistor 732 and a local supply node 736. Between the loadinductor 734 and the drain of the second n-channel transistor 732 is theoutput 735 of the radio frequency integrated circuit (RFIC) 704, whichmay be provided to a downconverter. The local supply node 736 may becoupled to the positive supply voltage pad 706 via a coupling wire thatincludes a parasitic resistance 744 a and a parasitic inductance 746 a.Because the passive components in an integrated circuit (e.g., theinductors) are typically much larger than the active components (e.g.,the transistors), the wires used to couple components on the radiofrequency integrated circuit (RFIC) 704 may include significantparasitic resistance and significant parasitic capacitance (depending onthe length of coupling wires).

The cathode of the −ve diode 722 may be coupled to the local supply node736 via a coupling wire that includes a parasitic inductance 746 b and aparasitic resistance 744 b. The anode of the −ve diode 722 may becoupled to the input signal pad 708. The voltage at the input signal pad708 may be the voltage Vin. The input signal pad 708 may also be coupledto the cathode of the +ve diode 724. The anode of the +ve diode 724 maybe coupled to a local ground node 740 via a coupling wire that includesa parasitic resistance 744 c and a parasitic inductance 746 c. Thevoltage at the anode of the +ve diode 724 may be referred to as thediode ground 747. The voltage at the local ground node 740 may bereferred to as Vgnd.

The ground pad 710 may be coupled to the local ground node 740 via acoupling wire that includes a parasitic resistance 744 d and a parasiticinductance 746 d. The degeneration inductor 738 may be coupled betweenthe local ground node 740 and the source of the first n-channeltransistor 730. The input signal pad 708 may also be coupled to the gateof the first n-channel transistor 730. The body of the first n-channeltransistor 730 may be coupled to the anode of a parasitic diode DNW 756.The cathode of the parasitic diode DNW 756 may be coupled to the localsupply node 736. The body of the first n-channel transistor 730 may alsobe coupled to the anode of a parasitic diode PW 754. The cathode of theparasitic diode PW 754 may be coupled to the source of the firstn-channel transistor 730. The body of the first n-channel transistor 730may be coupled to the local ground node 740 via a coupling wire thatincludes a parasitic resistance 744 e and a parasitic inductance 746 e.

Here, the parasitic diode DNW 756 represents the p-n junction diodeformed between the p-type body and the n-type nwell. The parasitic diodepsub 358 represents the p-n junction diode formed between the p-typesubstrate and the deep nwell.

The anode of the +ve diode 724 may be coupled to the anode of aparasitic diode psub 758. The cathode of the parasitic diode psub 758may be coupled to the cathode of the parasitic diode DNW 756.

The drain of the first n-channel transistor 730 may be coupled to thesource of the second n-channel transistor 732. The RC clamp 720 may becoupled between the local supply node 736 and the local ground node 740.A parasitic capacitance Cgs 742 may occur between the source of thefirst n-channel transistor 730 and the gate of the first n-channeltransistor 730.

The gate of the G1 cascode device 726 may be coupled to the RC clamptrigger voltage 760 from the RC clamp 720. The source of the G1 cascodedevice 726 may be coupled to the source of the second n-channeltransistor 732. The drain of the G1 cascode device 726 may be coupled tothe local supply node 736.

In a −ve charged-device model (CDM) event, the voltage between the gateand the source of the first n-channel transistor 730 builds up largervalues than during a +ve charged-device model (CDM) event, since thecharged-device model (CDM) discharge current needs to flow through the−ve diode 722, the RC clamp 720 and the parasitic inductances 746. Thecurrent through the degeneration inductor 738 is small; consequentlythere is not much voltage drop across the degeneration inductor 738.Instead, the entire voltage (or most of it) appears across the parasiticcapacitance Cgs 742, causing the amplifier 728 to fail.

If the gate of the main cascode (i.e., the second n-channel transistor732) is coupled to the RC clamp trigger voltage 760, the −vecharged-device model (CDM) event may turn on the amplifier 728,increasing the source potential of the first re-channel transistor 730,and thereby protecting the gate-to-source of the first n-channeltransistor 730. In this implementation, the load inductor 734 limits thecurrent.

If the gate of the G1 cascode device 726 is coupled to the RC clamptrigger voltage 760, the −ve charged-device model (CDM) event may turnon the amplifier 728, increasing the source potential of the firstn-channel transistor 730, and thereby protecting the gate-to-source ofthe first n-channel transistor 730. Because the G1 cascode device 726 isused instead of the main cascode, the current is not limited by the loadinductor 734, leading to a substantial improvement in charged-devicemodel (CDM) performance. The charged-device model (CDM) performance maybe better than the improvements seen with forward based diodes. Thus,the G1 cascode device 726 is the preferred option for 28 nanometer (nm)and lower technology nodes.

FIG. 8 is a graph illustrating −ye charged-device model (CDM) voltagesfor normal charged-device model (CDM) protection circuitry and forcharged-device model (CDM) protection circuitry 112 that includes a G1cascode device 126. In the normal charged-device model (CDM) protectioncircuitry, during −ve charged-device model (CDM) testing, the voltageVgs 866 a swings almost as high as Vin−Vgnd 864 a, resulting in failureof the first n-channel transistor 730. In the charged-device model (CDM)protection circuitry 112 that includes a G1 cascode device 726, during−ve charged-device model (CDM) testing, the voltage Vgs 866 b is muchlower than Vin−Vgnd 864 b, preventing failure of the first n-channeltransistor 730.

FIG. 9 is a flow diagram of another method 900 for providingelectrostatic discharge (ESD) protection. Specifically, the method 900may provide electrostatic discharge (ESD) protection for −vecharged-device model (CDM) testing. The method 900 may be performed by aradio frequency integrated circuit (RFIC) 104 that includescharged-device model (CDM) protection circuitry 112. The charged-devicemodel (CDM) protection circuitry 112 may include a G1 cascode device126.

The radio frequency integrated circuit (RFIC) 104 may detect 902 a −vecharged-device model (CDM) voltage pulse at an input signal pad 108. Theradio frequency integrated circuit (RFIC) 104 may conduct 904 currentthrough a −ve diode 122 coupled between the input signal pad 108 and alocal supply node 736. The radio frequency integrated circuit (RFIC) 104may steer 906 −ve charged-device model (CDM) current to the ground pad110 via an RC clamp 720. The radio frequency integrated circuit (RFIC)104 may turn on 908 a cascode device using an RC clamp trigger voltage760 from the RC clamp 720. The cascode device may be a main cascode or aG1 cascode device 726. The radio frequency integrated circuit (RFIC) 104may turn on 910 the input device 128 using the cascode device. The radiofrequency integrated circuit (RFIC) 104 may maintain 912 a voltage fromthe gate of the input device 128 to the source of the input device 128that is below the failure point for the input device 128.

FIG. 10 is a circuit diagram of a radio frequency integrated circuit(RFIC) 1004 that includes both de-Q circuitry 1014 and a G1 cascodedevice 1026. The radio frequency integrated circuit (RFIC) 1004 of FIG.10 may be one configuration of the radio frequency integrated circuit(RFIC) 104 of FIG. 1. The radio frequency integrated circuit (RFIC) 1004of FIG. 10 does not include models of parasitics that may occur in anintegrated circuit. The radio frequency integrated circuit (RFIC) 1004may be a receiver low noise amplifier (LNA). The radio frequencyintegrated circuit (RFIC) 104 may also include an amplifier 1028 (i.e.,an input device 128), a positive supply voltage pad 1006, an inputsignal pad 1008, a ground pad 1010, a +ve diode 1024, a −ve diode 1022,an RC clamp 1020, a load inductor 1034 and a degeneration inductor 1038.The amplifier 1028 may include a first n-channel transistor 1030 and asecond n-channel transistor 1032. The second n-channel transistor 1032may be referred to as the main cascode device.

The load inductor 1034 may be coupled between the drain of the secondre-channel transistor 1032 and a local supply node 1036. Between theload inductor 1034 and the drain of the second n-channel transistor 1032is the output 1035 of the radio frequency integrated circuit (RFIC)1004, which may be provided to a downconverter. The positive supplyvoltage pad 1006 may also be coupled to the local supply node 1036. Thecathode of the −ve diode 1022 may also be coupled to the local supplynode 1036. The anode of the −ve diode 1022 may be coupled to the inputsignal pad 1008. The input signal pad 1008 may also be coupled to thecathode of the +ve diode 1024. The anode of the +ve diode 1024 may becoupled to a local ground node 1040. The input signal pad 1008 mayfurther be coupled to the gate of the first n-channel transistor 1030.The ground pad 1010 may also be coupled to the local ground node 1040.The degeneration inductor 1038 may be coupled between the source of thefirst n-channel transistor 1030 and the local ground node 1040.

The drain of the first n-channel transistor 1030 may be coupled to thesource of the second n-channel transistor 1032. The RC clamp 1020 may becoupled between the local supply node 1036 and the local ground node1040. The de-Q circuitry 1014 may include a resistor 1016 and a diode1018 in series. The diode 1018 may be reverse biased during normaloperation, with a negligible impact on the receiver performance. Theresistor 1016 may be coupled between the source of the first n-channeltransistor 1030 and the anode of the diode 1018. The cathode of thediode 1018 may be coupled to the gate of the first n-channel transistor1030.

The drain of the G1 cascode device 1026 may be coupled to the localsupply node 1036 (the G1 cascode device 1026 may be an n-channeltransistor). The source of the G1 cascode device 1026 may be coupled tothe source of the main cascode. The gate of the G1 cascode device 1026may be coupled to an RC clamp trigger voltage 1060 provided by the RCclamp 1020. The RC clamp trigger voltage 1060 may also be coupled to thegate of the main cascode (i.e., the gate of the second n-channeltransistor 1032). The function of the G1 cascode 1026 in the radiofrequency integrated circuit (RFIC) 1004 during a −ye charged-devicemodel (CDM) test is the same as that discussed above in relation to FIG.6. The function of the de-Q circuitry 1014 during a +ve charged-devicemodel (CDM) test is the same as that discussed above in relation to FIG.3.

FIG. 11 is a more detailed circuit diagram of a radio frequencyintegrated circuit (RFIC) 1104 that includes a forward biased diode1170. Specifically, the radio frequency integrated circuit (RFIC) 1104of FIG. 11 includes parasitics that are inherent in an integratedcircuit. The radio frequency integrated circuit (RFIC) 1104 may be areceiver low noise amplifier (LNA). The radio frequency integratedcircuit (RFIC) 1104 may include an amplifier (i.e., an input device128), a positive supply voltage pad 1106, an input signal pad 1108, aground pad 1110, a +ve diode 1124, a −ve diode 1122, an RC clamp 1120, aforward biased diode 1170, a load inductor 1134 and a degenerationinductor 1138. The amplifier may include a first n-channel transistor1130 and a second n-channel transistor 1132. The second n-channeltransistor 1132 may be referred to as the main cascode device. Theparasitics illustrated in FIG. 11 are only models and do not representactual components within the radio frequency integrated circuit (RFIC)1104. The −ve charged-device model (CDM) path 1162 is illustrated fromthe input signal pad 1108 to the ground pad 1110.

The load inductor 1134 may be coupled between the drain of the secondre-channel transistor 1132 and a local supply node 1136. Between theload inductor 1134 and the drain of the second n-channel transistor 1132is the output 1135 of the radio frequency integrated circuit (RFIC)1104, which may be provided to a downconverter. The local supply node1136 may be coupled to the positive supply voltage pad 1106 via acoupling wire that includes a parasitic resistance 1144 a and aparasitic inductance 1146 a. Because the passive components in anintegrated circuit (e.g., the inductors) are typically much larger thanthe active components (e.g., the transistors), the wires used to couplecomponents on the radio frequency integrated circuit (RFIC) 1104 mayinclude significant parasitic resistance and significant parasiticcapacitance (depending on the length of coupling wires).

The cathode of the −ve diode 1122 may be coupled to the local supplynode 1136 via a coupling wire that includes a parasitic inductance 1146b and a parasitic resistance 1144 b. The anode of the −ve diode 1122 maybe coupled to the input signal pad 1108. The voltage at the input signalpad 1108 may be the voltage Vin. The input signal pad 1108 may also becoupled to the cathode of the +ve diode 1124. The anode of the +ve diode1124 may be coupled to a local ground node 1140 via a coupling wire thatincludes a parasitic resistance 1144 c and a parasitic inductance 1146c. The voltage at the anode of the +ve diode 1124 may be referred to asthe diode ground node 1147. The voltage at the local ground node 1140may be referred to as Vgnd.

The ground pad 1110 may be coupled to the local ground node 1140 via acoupling wire that includes a parasitic resistance 1144 d and aparasitic inductance 1146 d. The degeneration inductor 1138 may becoupled between the local ground node 1140 and the source of the firstn-channel transistor 1130. The input signal pad 1108 may also be coupledto the gate of the first n-channel transistor 1130. The body of thefirst n-channel transistor 1130 may be coupled to the anode of aparasitic diode DNW 1156. The cathode of the parasitic diode DNW 1156may be coupled to the local supply node 1136. The body of the firstn-channel transistor 1130 may also be coupled to the anode of aparasitic diode PW 1154. The cathode of the parasitic diode PW 1154 maybe coupled to the source of the first n-channel transistor 1130. Thebody of the first re-channel transistor 1130 may be coupled to the localground node 1140 via a coupling wire that includes a parasiticresistance 1144 e and a parasitic inductance 1146 e.

The anode of the +ve diode 1124 may be coupled to the anode of aparasitic diode psub 1158. The cathode of the parasitic diode psub 1158may be coupled to the cathode of the parasitic diode DNW 1156.

The drain of the first n-channel transistor 1130 may be coupled to thesource of the second n-channel transistor 1132. The RC clamp 1120 may becoupled between the local supply node 1136 and the local ground node1140. A parasitic capacitance Cgs 1142 may occur between the source ofthe first n-channel transistor 1130 and the gate of the first n-channeltransistor 1130. The anode of the forward biased diode 1170 may becoupled to the input signal pad 1108. The cathode of the forward biaseddiode 1170 may be coupled to the body of the first n-channel transistor1130.

The forward biased diode 1170 may provide another way to clamp thevoltage between the gate of the first n-channel transistor 1130 and thebody of the first n-channel transistor 1130. This provides additionalprotection against breakdown of the first n-channel transistor 1130.During a −ve charged-device model (CDM) event, the input signal pad 1108(and thus the gate of the first n-channel transistor 1130) is at groundpotential, while the ground pad 1110 is charged to a voltage of −ve. Thebody of the first n-channel transistor 1130, which is shorted to thelocal ground node 1140, is also at a lower potential. Thus, the diode1170 is forward biased, helping to quickly charge up the local groundnode 1140, thereby reducing the potential difference between the gateand the diffusion regions of the first n-channel transistor 1130.Reducing the potential difference between the gate and the diffusionregions may also cause the PW diode 1154 to become forward biased, whichalso charges up the source of the first re-channel transistor 1130.

FIG. 12 illustrates certain components that may be included within awireless device 1201. The wireless device 1201 of FIG. 12 may be oneconfiguration of the wireless device 102 of FIG. 1. A wireless device1201 may also be referred to as, and may include some or all of thefunctionality of, an access point, a broadcast transmitter, a NodeB, anevolved NodeB, a base station, an access terminal, a mobile station, auser equipment (UE), etc. The wireless device 1201 includes a processor1203. The processor 1203 may be a general purpose single- or multi-chipmicroprocessor (e.g., an ARM), a special purpose microprocessor (e.g., adigital signal processor (DSP)), a microcontroller, a programmable gatearray, etc. The processor 1203 may be referred to as a centralprocessing unit (CPU). Although just a single processor 1203 is shown inthe wireless device 1201 of FIG. 12, in an alternative configuration, acombination of processors (e.g., an ARM and DSP) could be used.

The wireless device 1201 also includes memory 1205. The memory 1205 maybe any electronic component capable of storing electronic information.The memory 1205 may be embodied as random access memory (RAM), read-onlymemory (ROM), magnetic disk storage media, optical storage media, flashmemory devices in RAM, on-board memory included with the processor,EPROM memory, EEPROM memory, registers, and so forth, includingcombinations thereof

Data 1209 a and instructions 1207 a may be stored in the memory 1205.The instructions 1207 a may be executable by the processor 1203 toimplement the methods disclosed herein. Executing the instructions 1207a may involve the use of the data 1209 a that is stored in the memory1205. When the processor 1203 executes the instructions 1207 a, variousportions of the instructions 1207 b may be loaded onto the processor1203, and various pieces of data 1209 b may be loaded onto the processor1203.

The wireless device 1201 may also include a transmitter 1211 and areceiver 1213 to allow transmission and reception of signals to and fromthe wireless device 1201. The transmitter 1211 and receiver 1213 may becollectively referred to as a transceiver 1215. An antenna 1217 may beelectrically coupled to the transceiver 1215. The wireless device 1201may also include (not shown) multiple transmitters, multiple receivers,multiple transceivers and/or multiple antennas.

The wireless device 1201 may include a digital signal processor (DSP)1221. The wireless device 1201 may also include a communicationsinterface 1223. The communications interface 1223 may allow a user tointeract with the wireless device 1201.

The various components of the wireless device 1201 may be coupledtogether by one or more buses, which may include a power bus, a controlsignal bus, a status signal bus, a data bus, etc. For the sake ofclarity, the various buses are illustrated in FIG. 12 as a bus system1219.

The term “determining” encompasses a wide variety of actions and,therefore, “determining” can include calculating, computing, processing,deriving, investigating, looking up (e.g., looking up in a table, adatabase or another data structure), ascertaining and the like. Also,“determining” can include receiving (e.g., receiving information),accessing (e.g., accessing data in a memory) and the like. Also,“determining” can include resolving, selecting, choosing, establishingand the like.

The phrase “based on” does not mean “based only on,” unless expresslyspecified otherwise. In other words, the phrase “based on” describesboth “based only on” and “based at least on.”

The term “processor” should be interpreted broadly to encompass ageneral purpose processor, a central processing unit (CPU), amicroprocessor, a digital signal processor (DSP), a controller, amicrocontroller, a state machine and so forth. Under some circumstances,a “processor” may refer to an application specific integrated circuit(ASIC), a programmable logic device (PLD), a field programmable gatearray (FPGA), etc. The term “processor” may refer to a combination ofprocessing devices, e.g., a combination of a DSP and a microprocessor, aplurality of microprocessors, one or more microprocessors in conjunctionwith a DSP core, or any other such configuration.

The term “memory” should be interpreted broadly to encompass anyelectronic component capable of storing electronic information. The termmemory may refer to various types of processor-readable media such asrandom access memory (RAM), read-only memory (ROM), non-volatile randomaccess memory (NVRAM), programmable read-only memory (PROM), erasableprogrammable read-only memory (EPROM), electrically erasable PROM(EEPROM), flash memory, magnetic or optical data storage, registers,etc. Memory is said to be in electronic communication with a processorif the processor can read information from and/or write information tothe memory. Memory that is integral to a processor is in electroniccommunication with the processor.

The terms “instructions” and “code” should be interpreted broadly toinclude any type of computer-readable statement(s). For example, theterms “instructions” and “code” may refer to one or more programs,routines, sub-routines, functions, procedures, etc. “Instructions” and“code” may comprise a single computer-readable statement or manycomputer-readable statements.

The functions described herein may be implemented in software orfirmware being executed by hardware. The functions may be stored as oneor more instructions on a computer-readable medium. The terms“computer-readable medium” or “computer-program product” refers to anytangible storage medium that can be accessed by a computer or aprocessor. By way of example, and not limitation, a computer-readablemedium may comprise RAM, ROM, EEPROM, CD-ROM or other optical diskstorage, magnetic disk storage or other magnetic storage devices, or anyother medium that can be used to carry or store desired program code inthe form of instructions or data structures and that can be accessed bya computer. Disk and disc, as used herein, includes compact disc (CD),laser disc, optical disc, digital versatile disc (DVD), floppy disk andBlu-ray® disc where disks usually reproduce data magnetically, whilediscs reproduce data optically with lasers. It should be noted that acomputer-readable medium may be tangible and non-transitory. The term“computer-program product” refers to a computing device or processor incombination with code or instructions (e.g., a “program”) that may beexecuted, processed or computed by the computing device or processor. Asused herein, the term “code” may refer to software, instructions, codeor data that is/are executable by a computing device or processor.

Software or instructions may also be transmitted over a transmissionmedium. For example, if the software is transmitted from a website,server, or other remote source using a coaxial cable, fiber optic cable,twisted pair, digital subscriber line (DSL), or wireless technologiessuch as infrared, radio and microwave, then the coaxial cable, fiberoptic cable, twisted pair, DSL, or wireless technologies such asinfrared, radio and microwave are included in the definition oftransmission medium.

The methods disclosed herein comprise one or more steps or actions forachieving the described method. The method steps and/or actions may beinterchanged with one another without departing from the scope of theclaims. In other words, unless a specific order of steps or actions isrequired for proper operation of the method that is being described, theorder and/or use of specific steps and/or actions may be modifiedwithout departing from the scope of the claims.

Further, it should be appreciated that modules and/or other appropriatemeans for performing the methods and techniques described herein, suchas those illustrated by FIG. 5 and FIG. 9, can be downloaded and/orotherwise obtained by a device. For example, a device may be coupled toa server to facilitate the transfer of means for performing the methodsdescribed herein. Alternatively, various methods described herein can beprovided via a storage means (e.g., random access memory (RAM),read-only memory (ROM), a physical storage medium such as a compact disc(CD) or floppy disk, etc.), such that a device may obtain the variousmethods upon coupling or providing the storage means to the device.Moreover, any other suitable technique for providing the methods andtechniques described herein to a device can be utilized.

It is to be understood that the claims are not limited to the preciseconfiguration and components illustrated above. Various modifications,changes and variations may be made in the arrangement, operation anddetails of the systems, methods and apparatus described herein withoutdeparting from the scope of the claims.

What is claimed is:
 1. An apparatus comprising: an input device; apositive supply voltage pad; an input signal pad; a ground pad; andcharged-device model protection circuitry configured to protect theinput device from electrostatic discharge, wherein the charged-devicemodel protection circuitry comprises a cascode device, and wherein thecascode device is triggered on by a trigger voltage.
 2. The apparatus ofclaim 1, wherein the charged-device model protection circuitry furthercomprises de-Q circuitry, wherein the de-Q circuitry comprises aresistor and a diode in series, wherein the input device comprises ann-channel transistor, wherein the resistor is coupled to a source of then-channel transistor, and wherein a cathode of the diode is coupled to agate of the n-channel transistor.
 3. The apparatus of claim 2, furthercomprising an inductor coupled between the source of the n-channeltransistor and the ground pad.
 4. The apparatus of claim 2, wherein thede-Q circuitry is configured to direct electrostatic discharge through a+ve diode coupled between the ground pad and the input signal pad. 5.The apparatus of claim 2, wherein the de-Q circuitry is configured tokeep a voltage from the gate of the n-channel transistor to the sourceof the n-channel transistor less than a voltage difference between theinput signal pad and a local ground node on the apparatus.
 6. Theapparatus of claim 1, wherein the cascode device is configured to turnon the input device during −ve electrostatic discharge.
 7. The apparatusof claim 6, wherein the cascode device comprises a first n-channeltransistor, wherein a gate of the first n-channel transistor is coupledto an RC clamp trigger voltage, and wherein a source of the firstn-channel transistor is coupled to a drain of the input device.
 8. Theapparatus of claim 7, wherein turning on the input device increases asource potential of the input device, protecting a gate-to-source of theinput device.
 9. A method for electrostatic discharge protection,comprising: detecting a −ve voltage pulse at an input signal pad;conducting current through a −ve diode coupled between the input signalpad and a local supply node; steering −ve current to a ground pad via anRC clamp; turning on a cascode device using an RC clamp trigger voltagefrom the RC clamp; turning on an input device using the cascode device;and maintaining a voltage from a gate of the input device to a source ofthe input device that is below a failure point for the input device. 10.The method of claim 9, wherein the cascode device comprises a cascodedevice, and wherein the cascode device turns on the input device during−ve electrostatic discharge.
 11. The method of claim 10, wherein thecascode device comprises a first n-channel transistor, wherein a gate ofthe first n-channel transistor is coupled to the RC clamp triggervoltage, and wherein a source of the first n-channel transistor iscoupled to a drain of the input device.
 12. The method of claim 10,wherein turning on the input device increases a source potential of theinput device, protecting a gate-to-source of the input device.
 13. Themethod of claim 9, further comprising comprising: detecting a +vevoltage pulse at a ground pad; conducting current through a +ve diodecoupled between the ground pad and the input signal pad; generating avoltage drop across a degeneration inductor coupled between the inputdevice and the ground pad; and limiting current passing from the sourceof the input device to the gate of the input device using de-Qcircuitry.
 14. The method of claim 13, wherein the de-Q circuitrycomprises a resistor and a diode in series, wherein the input devicecomprises an n-channel transistor, wherein the resistor is coupled to asource of the n-channel transistor, and wherein a cathode of the diodeis coupled to a gate of the n-channel transistor.
 15. The method ofclaim 14, wherein the de-Q circuitry directs electrostatic dischargethrough the +ve diode.
 16. An apparatus for electrostatic dischargeprotection, comprising: means for detecting a −ve voltage pulse at aninput signal pad; means for conducting current through a −ve diodecoupled between the input signal pad and a local supply node; means forsteering −ve current to a ground pad via an RC clamp; means for turningon a cascode device using an RC clamp trigger voltage from the RC clamp;means for turning on an input device using the cascode device; and meansfor maintaining a voltage from a gate of the input device to a source ofthe input device that is below a failure point for the input device. 17.The apparatus of claim 16, wherein the cascode device is configured toturn on the input device during −ve electrostatic discharge.
 18. Theapparatus of claim 17, wherein the cascode device comprises a firstre-channel transistor, wherein a gate of the first n-channel transistoris coupled to the RC clamp trigger voltage, and wherein a source of thefirst n-channel transistor is coupled to a drain of the input device.19. The apparatus of claim 17, wherein turning on the input deviceincreases a source potential of the input device, protecting agate-to-source of the input device.